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Espressif Systems /ESP32-C3 /UART0 /INT_ST

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Interpret as INT_ST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RXFIFO_FULL_INT_ST)RXFIFO_FULL_INT_ST 0 (TXFIFO_EMPTY_INT_ST)TXFIFO_EMPTY_INT_ST 0 (PARITY_ERR_INT_ST)PARITY_ERR_INT_ST 0 (FRM_ERR_INT_ST)FRM_ERR_INT_ST 0 (RXFIFO_OVF_INT_ST)RXFIFO_OVF_INT_ST 0 (DSR_CHG_INT_ST)DSR_CHG_INT_ST 0 (CTS_CHG_INT_ST)CTS_CHG_INT_ST 0 (BRK_DET_INT_ST)BRK_DET_INT_ST 0 (RXFIFO_TOUT_INT_ST)RXFIFO_TOUT_INT_ST 0 (SW_XON_INT_ST)SW_XON_INT_ST 0 (SW_XOFF_INT_ST)SW_XOFF_INT_ST 0 (GLITCH_DET_INT_ST)GLITCH_DET_INT_ST 0 (TX_BRK_DONE_INT_ST)TX_BRK_DONE_INT_ST 0 (TX_BRK_IDLE_DONE_INT_ST)TX_BRK_IDLE_DONE_INT_ST 0 (TX_DONE_INT_ST)TX_DONE_INT_ST 0 (RS485_PARITY_ERR_INT_ST)RS485_PARITY_ERR_INT_ST 0 (RS485_FRM_ERR_INT_ST)RS485_FRM_ERR_INT_ST 0 (RS485_CLASH_INT_ST)RS485_CLASH_INT_ST 0 (AT_CMD_CHAR_DET_INT_ST)AT_CMD_CHAR_DET_INT_ST 0 (WAKEUP_INT_ST)WAKEUP_INT_ST

Description

Masked interrupt status

Fields

RXFIFO_FULL_INT_ST

This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
TXFIFO_EMPTY_INT_ST

This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.
PARITY_ERR_INT_ST

This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
FRM_ERR_INT_ST

This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
RXFIFO_OVF_INT_ST

This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
DSR_CHG_INT_ST

This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
CTS_CHG_INT_ST

This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
BRK_DET_INT_ST

This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
RXFIFO_TOUT_INT_ST

This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
SW_XON_INT_ST

This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
SW_XOFF_INT_ST

This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
GLITCH_DET_INT_ST

This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
TX_BRK_DONE_INT_ST

This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
TX_BRK_IDLE_DONE_INT_ST

This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.
TX_DONE_INT_ST

This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
RS485_PARITY_ERR_INT_ST

This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.
RS485_FRM_ERR_INT_ST

This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.
RS485_CLASH_INT_ST

This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
AT_CMD_CHAR_DET_INT_ST

This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.
WAKEUP_INT_ST

This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd